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MITSUBISHI SEMICONDUCTOR
PS21963-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE INSULATED TYPE
PS21963-4
INTEGRATED POWER FUNCTIONS
600V/10A low-loss 5th generation IGBT inverter bridge for three phase DC-to-AC power conversion
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
* * * * * For upper-leg IGBTS :Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection. For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a UV fault (Lower-side supply). Input interface : 3V, 5V line (High Active). UL Approved : Yellow Card No. E80276
APPLICATION AC100V~200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES (PS21963-4)
38 0.5 20x1.778(=35.56) 35 0.3 A B TERMINAL CODE 3.5 16-0.5 1.5 0.05 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. NC VUFB VVFB VWFB UP VP WP VP1 VNC * UN VN WN VN1 FO CIN VNC * NC NC NC N W V U P NC
Dimensions in mm
0.28 1.778 0.2
17
1
(1)
14.4 0.5
0.4
14.4 0.5
.6 R1 2-
QR Code
3 MIN
Type name Lot No.
29.2 0.5
24 0.5
(3.5)
0.8 HEAT SINK SIDE
12
18 0.28 2.54 0.2 14x2.54 (=35.56) 0.5 0.5 0.5
25
8-0.6
4-C1.2
(3.3)
2.5 MIN 0.5 (2.656)
(0~5)
0.4
1.5 M
IN
9.50.5
5.50.5
(1.2) (2.756) DETAIL A
HEAT SINK SIDE
(1.2)
DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and leave another one open.
Aug. 2007
MITSUBISHI SEMICONDUCTOR
PS21963-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 2 LONG TERMINAL TYPE PACKAGE OUTLINES (PS21963-4A)
38 20x1.778(=35.56) 35 0.3
0.5
Dimensions in mm
A
B TERMINAL CODE 3.5 16-0.5
(1)
0.28 1.778 0.2
1.5 0.05
0.4
17
1
14.4 0.5
.6 R1 2-
QR Code
3 MIN
Type name Lot No.
0.8 HEAT SINK SIDE
18 0.28 2.54 0.2 14x2.54 (=35.56) 0.5 0.5 0.5
25 8-0.6 4-C1.2
0.4
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25.
NC VUFB VVFB VWFB UP VP WP VP1 VNC * UN VN WN VN1 FO CIN VNC * NC NC NC N W V U P NC
14.4 0.5
12
29.4 0.5
24 0.5
(3.5)
(3.3)
0.5
2.5 MIN
(0~5)
1.5 M
(2.656)
140.5
IN
5.50.5
(1.2) (2.756) DETAIL A
HEAT SINK SIDE
(1.2)
DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and leave another one open.
Fig. 3 ZIGZAG TERMINAL TYPE PACKAGE OUTLINES (PS21963-4C)
38 0.5 20x1.778(=35.56) 35 0.3 A B 3.5 1.5 0.05 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25.
Dimensions in mm
TERMINAL CODE NC VUFB VVFB VWFB UP VP WP VP1 VNC * UN VN WN VN1 FO CIN VNC * NC NC NC N W V U P NC
17
1
(1)
18.9
0.5
14.4 0.5
33.70.5
2-
14.4 0.5
12
R1
.6
QR Code
3 MIN
Type name Lot No.
29.2 0.5
24 0.5
(3.5)
0.8 HEAT SINK SIDE
0.4
0.4
0.28 1.778 0.2
16-0.5
18 0.28 2.54 0.2 14x2.54 (=35.56)
25 8-0.6 4-C1.2
0.5 0.5 0.5 (2.656)
(0~5)
(0~5)
0.4
1.5 M
IN
0.5
5.50.5
(1.2) (2.756) DETAIL A
HEAT SINK SIDE
(1.2)
9.5
DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and leave another one open.
Aug. 2007 2
MITSUBISHI SEMICONDUCTOR
PS21963-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 4 BOTH SIDES ZIGZAG TERMINAL TYPE PACKAGE OUTLINES (PS21963-4W)
38 20x1.778(=35.56) 35 0.3
0.5
Dimensions in mm
A
B 3.5 1.5 0.05 TERMINAL CODE 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. NC VUFB VVFB VWFB UP VP WP VP1 VNC * UN VN WN VN1 FO CIN VNC * NC NC NC N W V U P NC
17
1
(1)
17.4 0.5 14.4 0.5
35.2 0.6
2-
17.4 0.5 14.4 0.5
12
R1
.6
QR Code
3 MIN
Type name Lot No.
29.2 0.5
24 0.5
(3.5)
0.8 HEAT SINK SIDE
(1.8)
14x2.54 (=35.56) 0.5 0.5 0.5
2.5 MIN
(0~5)
0.28 2.54 0.25
7-0.6
4-C1.2
(0~5)
18
25
0.4
0.4 0.4
0.4
0.28 1.778 0.25
16-0.5
1.5 M
(2.656)
IN
110.5
5.50.5
(1.2) (2.756) DETAIL A
HEAT SINK SIDE
(1.2)
DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and leave another one open.
Fig. 5 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
CBU- CBV- CBU+ CBW- CBV+ CBW+
C1 : Electrolytic type with good temperature and frequency characteristics (Note : The capacitance value depends on the PWM control scheme used in the applied system). C2 : 0.22~2F R-category ceramic capacitor for noise filtering.
High-side input (PWM) (3V, 5V line)(Note 1, 2)
Input signal conditioning Level shifter
Protection circuit (UV)
Input signal conditioning Level shifter
Input signal conditioning Level shifter
C2 C1 (Note 6)
(Note 5)
Inrush current limiter circuit
P
Drive circuit
Drive circuit
Drive circuit
H-side IGBTS
DIP-IPM
AC line input
(Note 4)
U V W
(Note 7)
M
AC line output
Z
C VNC
N1
N
L-side IGBTS
CIN
Z : ZNR (Surge absorber) C : AC filter (Ceramic capacitor 2.2~6.5nF) (Note : Additionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment).
Drive circuit
Input signal conditioning
Fo logic
Protection Control supply circuit Under-Voltage
protection
Low-side input (PWM) FO (3V, 5V line)(Note 1, 2) Fault output (5V line) (Note 3)
(Note 6)
VNC VD
(15V line)
Note1: 2: 3: 4:
5: 6: 7:
Input logic is high-active. There is a 3.3k (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the input threshold voltage. By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 11) This output is open drain type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10k resistor. (see also Fig. 11) The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22F, high voltage type) is recommended to be mounted close to these P & N1 DC power input pins. High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction. Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.
Aug. 2007 3
MITSUBISHI SEMICONDUCTOR
PS21963-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 6 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
Drive circuit
P
Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault.
IC (A)
SC Protection Trip Level
H-side IGBTS
U V W
L-side IGBTS
External protection circuit N1
Shunt Resistor (Note 1)
A
N VNC CIN B
Drive circuit
Collector current waveform
CR
C
Protection circuit
(Note 2)
0 2 tw (s)
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0s. 2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
MAXIMUM RATINGS (Tj = 25C, unless otherwise noted) INVERTER PART
Symbol VCC VCC(surge) VCES IC ICP PC Tj Parameter Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Condition Applied between P-N Applied between P-N TC = 25C TC = 25C, less than 1ms TC = 25C, per 1 chip (Note 1) Ratings 450 500 600 10 20 27.0 -20~+125 Unit V V V A A W C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150C (@ TC 100C). However, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125C (@ TC 100C).
CONTROL (PROTECTION) PART
Symbol VD VDB VIN VFO IFO VSC Parameter Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage Condition Applied between VP1-VNC, VN1-VNC Applied between VUFB-U, VVFB-V, VWFB-W Applied between UP, VP, WP, UN, VN, WN-VNC Applied between FO-VNC Sink current at FO terminal Applied between CIN-VNC Ratings 20 20 -0.5~VD+0.5 -0.5~VD+0.5 1 -0.5~VD+0.5 Unit V V V V mA V
Aug. 2007 4
MITSUBISHI SEMICONDUCTOR
PS21963-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE INSULATED TYPE
TOTAL SYSTEM
Parameter VCC(PROT) Self protection supply voltage limit (short circuit protection capability) Module case operation temperature TC Tstg Storage temperature Viso Isolation voltage Symbol Condition VD = 13.5~16.5V, Inverter part Tj = 125C, non-repetitive, less than 2s (Note 2) 60Hz, Sinusoidal, 1 minute, Between pins and heat-sink plate Ratings 400 -20~+100 -40~+125 1500 Unit V C C Vrms
Note 2: TC measurement point
Control terminals
DIP-IPM
11.6mm
3mm
IGBT chip position FWD chip position Power terminals
TC point Heat sink side
THERMAL RESISTANCE
Symbol Rth(j-c)Q Rth(j-c)F Parameter Junction to case thermal resistance (Note 3) Condition Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) Min. -- -- Limits Typ. -- -- Max. 3.7 4.5 Unit C/W C/W
Note 3 : Grease with good thermal conductivity should be applied evenly with about +100m~+200m on the contacting surface of DIP-IPM and heat-sink. The contacting thermal resistance between DIP-IPM case and heat sink (Rth(c-f)) is determined by the thickness and the thermal conductivity of the applied grease. For reference, Rth(c-f) (per 1/6 module) is about 0.3C/W when the grease thickness is 20m and the thermal conductivity is 1.0W/m*k.
ELECTRICAL CHARACTERISTICS (Tj = 25C, unless otherwise noted) INVERTER PART
Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Parameter Collector-emitter saturation voltage FWD forward voltage Condition IC = 10A, Tj = 25C VD = VDB = 15V VIN = 5V IC = 10A, Tj = 125C Tj = 25C, -IC = 10A, VIN = 0V VCC = 300V, VD = VDB = 15V IC = 10A, Tj = 125C, VIN = 0 5V Inductive load (upper-lower arm) Collector-emitter cut-off current Tj = 25C Tj = 125C Min. -- -- -- 0.60 -- -- -- -- -- -- Limits Typ. 1.70 1.80 1.70 1.10 0.30 0.40 1.50 0.50 -- -- Max. 2.20 2.30 2.20 1.70 -- 0.60 2.10 0.80 1 10 Unit V V s s s s s mA
Switching times
VCE = VCES
Aug. 2007 5
MITSUBISHI SEMICONDUCTOR
PS21963-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE INSULATED TYPE
CONTROL (PROTECTION) PART
Symbol Parameter VD = VDB = 15V VIN = 5V VD = VDB = 15V VIN = 0V Condition Total of VP1-VNC, VN1-VNC VUFB-U, VVFB-V, VWFB-W Total of VP1-VNC, VN1-VNC VUFB-U, VVFB-V, VWFB-W VSC = 0V, FO terminal pull-up to 5V by 10k VSC = 1V, IFO = 1mA Tj = 25C, VD = 15V (Note 4) VIN = 5V Trip level Reset level Tj 125C Trip level Reset level (Note 5) Min. -- -- -- -- 4.9 -- 0.43 0.70 10.0 10.5 10.3 10.8 20 -- 0.8 0.35 Limits Typ. -- -- -- -- -- -- 0.48 1.00 -- -- -- -- -- 2.1 1.3 0.65 Max. 2.80 0.55 2.80 0.55 -- 0.95 0.53 1.50 12.0 12.5 12.5 13.0 -- 2.6 -- -- Unit mA mA mA mA V V V mA V V V V s V V V
ID
Circuit current
VFOH VFOL VSC(ref) IIN UVDBt UVDBr UVDt UVDr tFO Vth(on) Vth(off) Vth(hys)
Fault output voltage Short circuit trip level Input current Control supply under-voltage protection Fault output pulse width ON threshold voltage OFF threshold voltage ON/OFF threshold hysteresis voltage
Applied between UP, VP, WP, UN, VN, WN-VNC
Note 4 : Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating. 5 : Fault signal is asserted corresponding to a short circuit or lower side control supply under-voltage failure.
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter Mounting torque Condition Mounting screw : M3 Recommended : 0.69 N*m (Note 6) (Note 7) Min. 0.59 -- -50 Limits Typ. -- 10 -- Max. 0.78 -- 100 Unit N*m g m
Weight Heat-sink flatness Note 6 : Plain washers (ISO 7089~7094) are recommended.
Note 7: Flatness measurement position
Measurement position
+-
4.6mm
DIP-IPM
Heat sink side
- +
Heat sink side
Aug. 2007 6
MITSUBISHI SEMICONDUCTOR
PS21963-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE INSULATED TYPE
RECOMMENDED OPERATION CONDITIONS
Symbol VCC VD VDB VD, VDB tdead fPWM IO Parameter Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency Allowable r.m.s. current Condition Applied between P-N Applied between VP1-VNC, VN1-VNC Applied between VUFB-U, VVFB-V, VWFB-W For each input signal, TC 100C TC 100C, Tj 125C VCC = 300V, VD = VDB = 15V, fPWM = 5kHz P.F = 0.8, sinusoidal PWM, (Note 8) fPWM = 15kHz Tj 125C, TC 100C (Note 9) Min. 0 13.5 13.0 -1 1.5 -- -- -- 0.5 0.5 -5.0 Limits Typ. 300 15.0 15.0 -- -- -- -- -- -- -- -- Max. 400 16.5 18.5 1 -- 20 5.0 Arms 3.0 -- -- 5.0 s V Unit V V V V/s s kHz
PWIN(on) Allowable minimum input PWIN(off) pulse width
VNC variation VNC Between VNC-N (including surge) Note 8 : The allowable r.m.s. current value depends on the actual application conditions. 9 : IPM might not make response if the input signal pulse width is less than the recommended minimum value.
Fig. 7 THE DIP-IPM INTERNAL CIRCUIT
VUFB
HVIC IGBT1 Di1
DIP-IPM
P
VUB
VP1 UP VNC
VCC
UP
COM
UOUT
VUS
U
VVFB VP
VVB VP
IGBT2
VOUT VVS
Di2
V
VWFB WP
VWB WP
IGBT3
WOUT VWS
Di3
W IGBT4 Di4
LVIC
UOUT
VN1
VCC
IGBT5
VOUT
Di5
UN VN WN
Fo
UN VN WN Fo WOUT CIN VNO
IGBT6
Di6
VNC
GND
N
CIN
Aug. 2007 7
MITSUBISHI SEMICONDUCTOR
PS21963-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 8 TIMING CHART OF THE DIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (Lower-side only with the external shunt resistor and CR filter)
a1. Normal operation : IGBT ON and carrying current. a2. Short circuit detection (SC trigger). a3. IGBT gate hard interruption. a4. IGBT turns OFF. a5. FO outputs (tFO(min) = 20s). a6. Input "L" : IGBT OFF. a7. Input "H" : IGBT ON. a8. IGBT OFF in spite of input "H".
Lower-side control input Protection circuit state SET
a6 a7
RESET
Internal IGBT gate a2 a1 Output current Ic Sense voltage of the shunt resistor SC
a3
a4 a8 SC reference voltage
CR circuit time constant DELAY Error output Fo a5
[B] Under-Voltage Protection (Lower-side, UVD)
b1. Control supply voltage rising : After the voltage level reaches UVDr, the circuits start to operate when next input is applied. b2. Normal operation : IGBT ON and carrying current. b3. Under voltage trip (UVDt). b4. IGBT OFF in spite of control input condition. b5. FO outputs (tFO 20s and FO outputs continuously during UV period). b6. Under voltage reset (UVDr). b7. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state UVDr
RESET
SET
RESET b6
Control supply voltage VD
b1
UVDt
b3 b4
b2 Output current Ic
b7
Error output Fo
b5
Aug. 2007 8
MITSUBISHI SEMICONDUCTOR
PS21963-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE INSULATED TYPE
[C] Under-Voltage Protection (Upper-side, UVDB)
c1. Control supply voltage rising : After the voltage level reaches UVDBr, the circuits start to operate when next input is applied. c2. Normal operation : IGBT ON and carrying current. c3. Under voltage trip (UVDBt). c4. IGBT OFF in spite of control input signal level, but there is no FO signal outputs. c5. Under voltage reset (UVDBr). c6. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state UVDBr Control supply voltage VDB
RESET
SET
RESET
c1
UVDBt
c5 c3 c4 c6
c2 Output current Ic High-level (no fault output) Error output Fo
Fig. 9 RECOMMENDED MCU I/O INTERFACE CIRCUIT
5V line
10k
DIP-IPM
UP,VP,WP,UN,VN,WN
MCU
Fo VNC(Logic)
Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and the wiring impedance of the printed circuit board. The DIP-IPM input section integrates a 3.3k (min) pull-down resistor. Therefore, when using an external filtering resistor, pay attention to the turn-on threshold voltage.
3.3k (min)
Fig. 10 WIRING CONNECTION OF SHUNT RESISTOR
DIP-IPM
Wiring inductance should be less than 10nH. Equivalent to the inductance of a copper pattern in dimension of width=3mm, thickness=100m, length=17mm
VNC N
Shunt resistor Please make the GND wiring connection of shunt resistor to the VNC terminal as close as possible.
Aug. 2007 9
MITSUBISHI SEMICONDUCTOR
PS21963-4/-4A/-4C/-4W
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 11 AN EXAMPLE OF TYPICAL DIP-IPM APPLICATION CIRCUIT
C1: Electrolytic capacitor with good temperature characteristics C2,C3: 0.22~2F R-category ceramic capacitor for noise filtering
C2 C1 C2 C1 C2 C1
VUFB HVIC VP1
C3 VCC UP VUB UOUT VUS
VVFB
VWFB
DIP-IPM
P
Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.
UP
U
VVB
VP
VP
VOUT VVS
V
M
VWB
WP VNC
WP
WOUT
Note 1 : Input drive is High-Active type. There is a 3.3k(min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and turn-off threshold voltage. 2 : Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible. 3 : FO output is open drain type. It should be pulled up to the positive side of a 5V power supply by a resistor of about 10k. 4 : To prevent erroneous protection, the wiring of A, B, C should be as short as possible. 5 : The time constant R1C4 of the protection circuit should be selected in the range of 1.5-2s. SC interrupting time might vary with the wiring pattern. Tight tolerance, temp-compensated type is recommended for R1, C4. 6 : All capacitors should be mounted as close to the terminals of the DIP-IPM as possible. (C1: good temperature, frequency characteristic electrolytic type, and C2, C3: good temperature, frequency and DC bias characteristic ceramic type are recommended.) 7 : To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible. Generally a 0.1-0.22F snubber between the P-N1 terminals is recommended. 8 : Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and leave another one open. 9 : It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction. 10 : If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended to connect control GND and power GND at only a point. Aug. 2007 10
MCU
5V line C3 15V line
COM VWS
W
LVIC
UOUT
VN1
VCC
VOUT
UN VN WN Fo
UN VN WN Fo WOUT
Long wiring here might cause short-circuit.
N
VNC
GND
C CIN
Long GND wiring here might generate noise to input and cause IGBT malfunction.
B C4 A
R1
Shunt resistor
N1
Long wiring here might cause SC level fluctuation and malfunction.

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